Miju LabsChip design is the niche that looks best in a one-line summary and worst in every subsequent line.
The summary: a $18B market growing to $28–31B by 2030, engineers earning $125,040 a year, a projected shortfall of 273,000 engineers by 2030, and exactly one company anywhere claiming the vertical. The subsequent lines: the highest-value training signal is already flowing into a tool vendor's repository, the experts are bound by the most aggressive IP assignment terms in this atlas, and you cannot produce a single verified RTL datapoint without a commercial simulator.
Cadence's JedAI platform "aggregates waveforms, coverage reports, timing analyses, and physical layouts into a unified training data repository, creating a compounding data moat" (SemiAnalysis). That is the decisive sentence. The valuable signal in chip design is not RTL source — it is verification and signoff telemetry, and it arrives in Cadence's hands as a by-product of software its customers already pay for. Synopsys runs the same play through AgentEngineer with AMD and Microsoft as named partners (Synopsys). The Big Three hold over 85% market share, with Synopsys at 84–85% of synthesis and 90%+ of PrimeTime signoff and Siemens above 85% of Calibre physical verification.
Compare Mechanical CAD and manufacturing, where Autodesk trained Bernini on public shapes and put $200M into an outside company rather than mine its own corpus. Same structural position, opposite behaviour, opposite conclusion.
What the data actually is
Verification judgement, and it is the one artefact in this atlas that cannot be produced without buying software first.
The valuable lines would be: a verification engineer's coverage-closure strategy, narrated; why this assertion and not that one; the debug trace from a failing regression and the sequence of hypotheses that resolved it; a physical-design engineer's read on why a timing path will not close and which fix costs least area. All of it is judgement about simulation output — which means every datapoint requires a simulator run, and every simulator run requires a licence.
The academic layer is unusually mature, which cuts against you rather than for you. VerilogEval (NVIDIA, with a 2025 TODAES revisit), RTLLM, CVDP (Comprehensive Verilog Design Problems, 2025) and ChipVerilog (OpenCores-derived, 2026) all exist (arXiv 2309.07544, arXiv 2308.05345, arXiv 2506.14074, arXiv 2607.13079). None is saturated. But "there is no benchmark" — the argument that opens Architecture, engineering and construction and Video, motion and VFX — is unavailable here.
Proof scores 2. Four public benchmarks already frame the domain, and there is no lab audience visibly waiting for a fifth.
Is anyone buying
Budget scores 2, and the honest position is that the research could not find a frontier-lab buyer at all.
[NOTHING FOUND]. No frontier-lab job posting for chip-design expert data. GDPval deliberately excludes chip design from its 44 occupations (OpenAI). The RL-environment directory's own summary states that no vendor in it focuses primarily on chip design (rl-list). No lab publishes anything citing RTL expert data.
The Senior code review page in this atlas notes that Anthropic is hiring a Research Engineer, Chip Design RL (Anthropic) — a role title that names this domain. That posting sits directly against this section's [NOTHING FOUND].
Both can be true. An RL research engineer builds training systems in-house; a subject-matter-expert req buys practitioner judgement. Investment banking and financial modelling shows a lab doing the second and Offensive security shows it doing both. Chip design so far shows only the first — which is evidence a lab cares about the domain, and evidence it intends to serve that interest with its own engineers. It moves budget from 1 to 2. It does not make a market.
The buyers who do exist are the wrong shape: Cadence, Synopsys, Siemens and NVIDIA, plus well-funded application companies — ChipAgents (Alpha Design AI), Series A extended to $134M with Micron and MediaTek participating on reported 6x ARR growth (TechFundingNews); Cognichip at $60M (TechCrunch); Architect Labs at $24M (SiliconANGLE); Bronco AI and ChipStack in verification [WEAK] (SemiWiki). A small set of extremely sophisticated customers who mostly generate their own data and sit downstream of vendors who already own the telemetry.
Getting the experts
Reach scores 3, the lowest in this set. There is no register: an RTL engineer holds no licence, and the credential is employment history at companies who will not confirm it.
The channels are conferences and forums: DAC at roughly 6,300 attendees [WEAK — stale 2018 figure], DVCon, SemiWiki, Verification Academy, r/chipdesign, EDABoard. Real communities, small, and none of them a searchable list of verified practitioners the way NASBA is for CPAs (Accounting, audit and tax) or NCEES is for engineers (Architecture, engineering and construction).
BLS counts 297,900 US electrical and electronics engineers at $125,040/yr, $60.12/hr (BLS Occupational Outlook Handbook; no URL was captured in the research). The historical semiconductor engineering population is around 418,000 with the 273,000-engineer shortfall by 2030 projected against it — which means the people you want are the most in-demand engineers in the country, and their employers know it.
What it costs to run
Cost scores 1. This is the clearest tool-licence disqualifier in the research.
Fabless companies spend $80–150K per engineer per year on tools, IP and verification; IDMs spend $40–80K (SemiAnalysis). You cannot generate execution-verified RTL data without a simulator, and commercial simulators are enterprise-priced with negotiated seat counts. Open-source alternatives — Verilator, Yosys, OpenROAD — exist and are genuinely capable, but they do not reflect the commercial flows that labs and EDA customers would pay to model.
Set that next to the labour line. Your expert costs perhaps $120/hr. Your tooling costs, on a per-engineer-year basis, somewhere between $80,000 and $150,000. The dominant cost in this business is a licence, not an hour — which inverts the entire economic logic every other page in this atlas relies on, and which no small operator can carry before revenue.
Compare Mechanical CAD and manufacturing at low thousands per seat, Video, motion and VFX at a per-seat commercial NLE, Architecture, engineering and construction at seats plus code books. This is a different order of magnitude and a different kind of business.
Who is already there
Room scores 4 — high, and unreliable.
Phinity Labs is the only vertical chip-design environment company found anywhere: a "domain-specific environment play for chip-design and technical optimization workflows" out of Pear VC's PearX S25 batch, hiring a Founding Senior RTL Design or DV Engineer in San Francisco (alignlist, LinkedIn posting).
Phinity Labs' funding, investors and customers could not be confirmed from any primary source. PitchBook, Tracxn and Caplight profiles exist but are paywalled or robots-blocked; the evidence here is a directory description plus job postings [WEAK]. The room score of 4 is therefore a score on an unknown. If chip design is under serious consideration, this needs a direct conversation or a paid data pull before anything else — it is the one fact that could turn a 4 into a 2.
Defense scores 3. The supply genuinely stays scarce — the shortfall is structural and the skill takes a decade — and verification methodology churns with each process node. But defensibility against Cadence is nil, because the asset that matters is not the one you would be assembling.
What would kill it
IP assignment, which is the worst regime in the atlas. Semiconductor invention-assignment agreements bite on scope, not just time and resources: they capture off-hours work "related to company business", which for a chip engineer covers "wireless communication, IoT device design, ML inference hardware, automotive compute, power management circuitry". California Labor Code §2870's carve-out still fails where an invention "relate[s]... to the employer's business" — and Texas has no equivalent statute, being "one of the most employer-favorable IP assignment jurisdictions in the country". Austin is where much of the workforce sits, and RTL and verification side-work is called out as heightened risk (Promise Legal). Your experts largely cannot legally sell you what you want to buy.
Export control. EAR and ITAR deemed-export rules apply to semiconductor design technology shared with foreign nationals, and much of the available pool is on visas [WEAK — general legal guides, not a chip-data-specific ruling] (Young Basile).
The tool vendors have already won. JedAI is collecting the telemetry as a by-product. You would be assembling by hand what Cadence receives for free.
The first ninety days here
Do not spend them here. The combination that decides it is not the absence of a buyer alone, nor the licence cost alone, but the three together: no lab demand, a capital-dominated cost base, and a supply population that is contractually prevented from participating. Any one is survivable. All three is a different company.
If the domain still pulls, the cheapest disproof is two conversations: one with an employment lawyer about whether an Austin-based DV engineer can legally moonlight on RTL at all, and one with an EDA reseller about the smallest viable simulator seat. Both answers arrive in a week and both are likely to end the enquiry. See When to stop.
Where the record is thin
Phinity Labs is the largest hole and it is the load-bearing one — see the gap above.
DAC attendance is a stale 2018 figure. The BLS electrical-engineering numbers arrive without a captured URL. The export-control claim rests on general legal guides rather than a chip-data-specific ruling. And the [NOTHING FOUND] on lab demand sits in unresolved tension with Anthropic's Chip Design RL req — the negative is a negative from job-board searching, which is a weaker instrument than it looks.